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Why build your own SSD Controller?

by Hu Yoshida on Sep 5, 2012

Last month Hitachi Data Systems announced its vision and roadmap for an end-to-end flash ecosystem for the enterprise. By flash we are specifically addressing the higher density MLC (multi-level cell) NAND flash, which is typically associated with consumer-grade devices because of its lower durability and slower performance compared to SLC (single-level cell) NAND flash. If MLC is less durable and slower than SLC NAND flash, why is HDS, with its reputation for highly reliable enterprise storage systems, choosing to go with MLC?

One reason is that the consumer market has adopted MLC, and the volumes in the consumer space are driving the costs down much faster than the cost of SLC, which is usually reserved for the low volume enterprise market. By adopting MLC we can ride the price erosion curve that is being driven by the consumer space and apply it to reducing costs in the enterprise space.

However, the main reason is that HDS is able to provide enterprise-class availability and performance for MLC flash through the development of an enterprise flash controller.

While NAND flash is considered to be non-volatile, durability of the NAND cell degrades with every write and format (i.e. erase). While NAND can write cells at the page level, 8k for example, it must erase pages in larger blocks like 1 MB, and a write can only occur to a formatted page. Each rewrite to a page must occur to a new page causing fragmentation and requiring garbage collection. At some point a block will be filled with too many invalidated pages and will require clean up, which consists of moving the remaining valid pages to another block before reformatting the old block.  This activity degrades performance, which cannot be tolerated by an enterprise application that requires consistent high performance.

Once a cell is written, it’s considered non-volatile and able to retain its charge without a power source for some period of time. In reality the electrons in the floating gate will actually leak over time and need to be refreshed. The voltage applied to read the cell will also cause electrons to leak. Therefore, additional error correction code (ECC) must be added to ensure the data stored in the cells is read correctly until the signals deteriorate to such a level that the data needs to be reclaimed and moved to another block.

All these activities are handled by the flash controller at the firmware level and how these functions are executed have a major impact on NAND flash performance and availability. Functions performed by the controller include:

  • Page and Block mapping
  • Logical to physical mapping
  • Wear leveling
  • Read scrubbing
  • Read and write caching
  • Reclamation
  • Garbage collection
  • Extended error correction

The processing power, memory and bandwidth of a flash controller limit not only the performance and durability of a flash module, but also affect its capacity. While flash does not have the latencies of spinning disk, the latencies for house keeping increase with the increase in capacity. Due to the high cost of flash memory, current off the shelf flash controllers are designed with a single CPU with limited memory and bandwidth. This is fine for the consumer market but it is not enough for the demands of an enterprise data center.

The new flash controller developed by Hitachi, Ltd. is designed for the enterprise data center. Parallel processing is introduced to reduce latency with multi lanes of PCIe, a multi-core 1.0GHz CPU, integrated DDR-3 interface, integrated flash controller logic, and 32 paths to the flash array.  This increase in processing power and bandwidth along with more parallel operations will increase the performance of MLC by 4 times and will increase the durability to 5 years for enterprise workloads., The new controller will also enable the capacity to scale into terabytes. Hitachi has also added features like zero block compression for efficiency and secure erase for privacy. Because NAND flash always writes to a new page, erasing pages with the use of overwrites is no longer valid. These are just a few of the challenges that our engineers have solved with this enterprise flash controller.

You can expect to see this Hitachi flash controller being delivered to our enterprise platforms in the near future. As a first step we redesigned the VSP platform to handle the higher throughput of flash devices. This feature was announced last month as flash acceleration. While this feature is designed for flash devices it also increases the overall VSP performance through the creation of multiple threads and offloading of processor workloads.

Hitachi engineers have extensive experience in building intelligent controllers and back planes, which has been proven with innovative products like USP, USP V, VSP, AMS and HUS. Now they are applying this experience to building enterprise flash controllers which will soon appear in flash products throughout our portfolio.

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Comments (4 )

Tom Stevens on 06 Sep 2012 at 1:03 am

Excellent article. I have a question regarding Hitachi usage of PCIe enabled Flash. I presume this technology is for your storage class arrays but I have clients inquiring about Hitachi Compute blade [with your 8 x PCIe available slots] and usage of PCIe enabled flash cards to meet business analytic’s use case. Does Hitachi have partnership with vendors like Fusion-io to include their cards in a configuration.

[Apologies if wrong place to post question, I couldn't find your community site to post the question which is odd]

Hu Yoshida on 13 Sep 2012 at 12:17 pm

We do offer Fusion IO PCIe cards with our CB 2000 Blade servers in selected solutions for Oracle and SAP HANA. These are not sold standalone. We are also testing other vendor products.

Jay on 14 Dec 2012 at 12:07 pm

Any idea when VSP will have capability to perform data dedupe or compression?

Hu Yoshida on 08 Jan 2013 at 4:43 pm

Hello Jay, thanks for the comment. I cannot discuss unannounced plans for our products; however, I can comment on what we already have in VSP. Dedupe and compression are two types of technologies for capacity efficiency. There are other types of capacity efficiency technologies that are more effective for active data that is being updated, moved or copied. One such technology is Zero Page Reclaim, where allocated pages that do not contain data are reclaimed from previously allocated storage space. This, in combination with the ability to attach and virtualize external storage, enables VSP to reclaim unused space from previously allocated volumes on any attached storage device. This is performed by moving the volume non-disruptively through VSP and identifying the allocated pages that do not have any data. These “thin provisioned” volumes can be updated, moved, copied, and expanded to their original allocation on demand. Since most volumes are over allocated, dedupe and compression will spend a lot of time deduping and compressing zero pages, and when the data needs to be updated, moved or copied, the data will need to be re-hydrated or un-compressed first.

We recently introduced compression in our Hitachi Accelerated Flash storage module, which can be allocated in VSP. The key to the Hitachi Accelerated Flash module is a multi-core processor that increases the performance, durability and capacity of MLC flash DIMMS. This processor controls the compression of writes to reduce the number of Write/Formats that affect the durability of MLC flash. It keeps track of the mapping of compressed pages to full pages and blocks so that any updates, moves or copies that are issued through VSP to Hitachi Accelerated Flash module are transparent to VSP.

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