Supercomputing 2010 Update and Observations
by Ken Wood on Nov 22, 2010
This year’s Supercomputing 2010 (SC10) event was held in New Orleans. The initial estimate on the attendance was approximately 13,500. Based on the other various conferences that I’ve attended in the past, mostly storage-focused, this has a lot of end users and “real customers” in attendance.
What I find very cool about this is that beyond vendors speaking and showing their (our) wares and services, many customers also have a large booth presence either showing their accomplishments, active projects or innovative research. Many of the top computer science programs at universities and system integrators attended, presented and exhibited their technologies and services.
General Purpose Graphic Processor Unit – GPGPU – and CPU combinations were everywhere. Previously, we’ve been referring to the integration of general purpose processors and GPGPU systems as hybrid computing platforms, but the dominate term used at the conference is “heterogeneous computing platform.” With heterogeneous computing platform solutions everywhere, NVIDIA was also everywhere. NVIDIA had their booth, but they also had a presence in one form or another at many other booths as well, including Hitachi’s booth. Hitachi also had other High Performance Computing solutions being showcased and used for supplementing conversations, but it primarily addresses the requirements of the Japanese HPC market.
I attended several of the storage related sessions, but spent a better portion of my time (actually spent the most time talking with customers and others on the exhibit floor) in the heterogeneous computing platform sessions and the programmability challenges customers and developers face. While it seems there is a tremendous interest and lots of experimentation in GPGPU computing, customers that I’ve talked to are waiting for an industry standard architecture to protect their investments before major porting efforts begin.
However, similar to most programming challenges (particularly in parallel and distributed architectures), the level of effort put into tuning code for the platform yields ever increasing results, but with diminishing returns on investment. That is, the first few levels or “passes” of a code porting/optimization effort will yield a fairly significant amount of noticeable “speedup” with a basic knowledge of the platform’s capabilities and semantic understanding. Greater platform understanding and deeper coding to the platform will result in increased performance, but requires greater effort. The art is to know when great enough is good enough. This leads to the “Holy Grail” of intelligent compilers that can make these optimizations for you.
Why is this interesting?
For one thing, the challenge to performance computing is not so much how fast can we process, but how efficiently. My opinion is, if money and power were no object, we could build much more powerful systems than we have today. However, money and power are huge hurdles and the kind of power needed to run these types of systems are difficult to deliver. I usually qualify many of my statements with “…based on today’s technology” when I talk of future solutions, because I believe we will find a way to overcome many of the challenges one way or another. At this time and for the foreseeable future, many believe that heterogeneous computing using GPGPU technology is one of the more promising approaches that is readily available to the mass development community.
I know the majority of the HDS blog readers come to this site researching storage related topics, but if any of you also have interest in computing architectures or are in the midst of GPGPU and heterogeneous computing platform projects, deployments, porting or research, I would be interested in hearing of any of your thoughts as I too am in research mode.